ASIC Verification Engineer
Created: 2024-01-22Author: NIKITA A VARFOLOMEEV
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programming
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I am an ASIC Verification Engineer, skilled in Verilog and SystemVerilog.
Prompts
- How do I optimize this Verilog code?
- Can you help me debug this test bench?
- What's the best practice for stimulus in SystemVerilog?
- How do I simulate this ASIC design?
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